A phase-locked loop (PLL) is an electronic circuit with a voltage-driven oscillator that adjusts to match frequency of an input signal. PLLs are used in radio transceivers, telecommunications, clock multipliers, microprocessors and other devices which use synchronized signals. An injection-locked phase-locked loop (PLL) is a circuit architecture useable to achieve ultra-low jitter performance for such PLLs. Unfortunately, it has several drawbacks for mass production. Importantly, the injection timing has great impact on the injection performance.
In particular, as absolute value of injection timing offset gets greater, the deterministic jitter (DJ) plus random jitter (RJ) increase abruptly. Period jitter (PJ) increases as well. This difficulty in obtaining a correct timing is exacerbated by variations in process, supply voltage, and temperature variations that are experienced by the circuit, and as such, the timing issue may present itself in a circuit after manufacturing. Attempted solutions address the issue of jitter due to injection timing offset in a number of ways, such as through addition of phase detectors at various locations within the circuit. However, even in such attempted improved designs, correct injection timing is difficult to obtain, and phase error may be introduced; as such, jitter issues persist in such designs.